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TMPR4955AF Datasheet(PDF) 140 Page - Toshiba Semiconductor

Part # TMPR4955AF
Description  64-Bit TX System RISC TX49 Family
PDF  168 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4955AF Datasheet(HTML) 140 Page - Toshiba Semiconductor

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Chapter 7 JTAG Interface
7-6
7.3.5
Test Access Port (TAP)
The Test Access Port (TAP) consists of the five signal pins: TRST
TRST
TRST
TRST* JTDI
JTDI
JTDI
JTDI, JTDO
JTDO
JTDO
JTDO, JTMS
JTMS
JTMS
JTMS,
and JTCK
JTCK
JTCK
JTCK. Serial test data and instructions are communicated over these five signal pins,
along with control of the test to be executed.
As Figure 7.3.7 shows, data is serially scanned into one of the four registers (
Instruction
register,
Bypass register, Device Identification register, or the Boundary-scan register)
from the JTDI
JTDI
JTDI
JTDI pin, or it is scanned from one of these four registers onto the JTDO
JTDO
JTDO
JTDO pin.
The JTMS
JTMS
JTMS
JTMS input controls the state transitions of the main TAP controller state machine.
The JTCK
JTCK
JTCK
JTCK input is a dedicated test clock that allows serial JTAG data to be shifted
synchronously, independent of any chip-specific or system clocks.
Figure 7.3.7 JTAG Test Access Port
Data on the JTDI
JTDI
JTDI
JTDI and JTMS
JTMS
JTMS
JTMS pins is sampled on the rising edge of the JTCK
JTCK
JTCK
JTCK input clock
signal. Data on the JTDO
JTDO
JTDO
JTDO pin changes on the falling edge of the JTCK
JTCK
JTCK
JTCK clock signal.
7.3.6
TAP Controller
The processor implements the 16-state TAP controller as defined in the IEEE JTAC
specification.
7.3.7
Controller Reset
The TAP controller state machine can be put into Reset state the following:
•
assertion of the TRST
TRST
TRST
TRST* signal (Low) resets the TAP controller.
•
keeping the JTMS
JTMS
JTMS
JTMS input signal asserted through five consecutive rising edges of
JTCK
JTCK
JTCK
JTCK input.
In either case, keeping JTMS
JTMS
JTMS
JTMS asserted maintains the Reset state.
JTCK
Data scanned out serially
JTD0 sampled on falling edge of
JTCK
JTMS and JTDI sampled on rising
edge of JTCK
Data scanned in serially
JTDI pin
JTMS pin
JTDO pin
0
0
7
Instruction register
Bypass register
86
Boundary-scan registe
0
0
0
7
Instruction register
Bypass register
86
Boundary-scan register
031
Device
Identification register
0



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