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GL3590 Datasheet(PDF) 24 Page - GENESYS LOGIC

Part # GL3590
Description  USB 3.1 Gen 2 Hub Controller
PDF  47 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL3590 Datasheet(HTML) 24 Page - GENESYS LOGIC

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GL3590 Datasheet
© 2020 Genesys Logic, Inc. - All rights reserved.
Page 24
GLI Confidential
AVDD10
4
7
6
9
8
P
1.0V power for analog PLL circuits
VP10_DIG
14, 54
6, 14, 52
5,13,54
8,16,
56
12,
45
P
1.0V power pins for digital circuits
VP10_PHY
57
55
57
59
48
P
1.0V power pins for analog circuits
VP10_RX
55
54
56
58
47
P
1.0V power pins for digital circuits
VP10_
MEM_A
53
51
53
55
44
P
1.0V internal memory group 1 power
pins
VP33_DIG
3,19, 52
5, 19, 49
4,18,52
7,21,
54
7,
17,
43
P
3.3V power pins for digital circuits
AVDD33
7
10
9
12
11
P
3.3V power for analog PLL circuits
VP33_U2
22, 35,
71, 86
23, 36,
72, 87
24,39,72,
87
1,27,
40,74
1,
21,
30,
62
P
Analog 3.3V power pins
VBUS
51
50
51
53
42
I
VBUS valid detection pin
VP33
58
56
58
60
49
P
3.3V power input
I2C Interface
Name
BGA289
BGA144
Type
Description
I2C_CLK
R5
J8
B
I2C clock for Hub as master or slave
I2C_DAT
C1
D5
B
I2C data for Hub as master or slave
I2C_CLK_M
ST
D17
E11
B
I2C clock for Hub as master
I2C_DAT_M
ST
E17
F11
B
I2C data for Hub as master
SMC
B8
D8
B
SMBus clock
SMD
R17
H10
B
SMBus data
I2C Interface
Name
QFN88
(OV3S1)
QFN88
(OV1S1)
QFN88
(OV6S1)
QFN88
(OV7S1)
QFN
76
Type
Description
I2C_CLK
-
22
21
24
20
B
I2C clock for Hub as master or slave
I2C_DAT
-
1
1
3
3
B
I2C data for Hub as master or slave
I2C_CLK
_MST
-
-
-
-
-
B
I2C clock for Hub as master
I2C_DAT
_MST
-
-
-
-
-
B
I2C data for Hub as master
SMC
-
62
62
64
52
B
SMBus clock
SMD
-
46
48
49
39
B
SMBus data



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