S71GS256 datasheet(117/195 Pages) SPANSION

117 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

117

Ad vance

Info rmat i o n

Bus Configuration Register

The BCR defines how the CellularRAM device interacts with the system memory

bus. Page mode operation is enabled by a bit contained in the RCR. Table 18

below describes the control bits in the BCR. At power up, the BCR is set to 9D4Fh.

Notes:

1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.

3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused

by refresh collisions require a corresponding number of additional CE# LOW cycles.

Figure 32. Configuration Register WRITE, Synchronous Mode Followed by READ0

Latch Control Register Value

ADDRESS

tHD

OPCODE

tSP

Latch Control Register Address

tSP

tHD

tSP

tHD

tCSP

tCBPH

(Note 3)

High-Z

tCEW

DATA

VALID

CLK

A[22:0]

(except A19)

A19

(Note 2)

CRE

ADV#

CE#

OE#

WE#

LB#/UB#

WAIT

DQ[15:0]

Don't care

Legend:

tSP

tHD

S71GS256 Datasheet(PDF) 117 Page - SPANSION

S71GS256 Datasheet(HTML) 117 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL