S71GS256 datasheet(121/195 Pages) SPANSION

121 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

121

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Info rmat i o n

Latency Counter (BCR[13:11]): Default = Three-Clock Latency

The latency counter bits determine how many clocks occur between the begin-

ning of a READ or WRITE operation and the first data value transferred. Latency

codes from two (three clocks) to six (seven clocks) are allowed (see Table 21 and

Figure 36 below).

Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is trans-

ferred on the next clock cycle.

Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 35.

Figure 34. WAIT Configuration (BCR[8] = 1)

Note: Non-default BCR setting: WAIT active LOW.

Figure 35. WAIT Configuration During Burst Operation

Table 21. Variable Latency Configuration Codes

BCR[13:11]

LATENCY

CONFIGURATION CODE

LATENCY (Note)

MAX INPUT CLK FREQUENCY (MHz)

NORMAL

REFRESH

COLLISION

70ns/80 MHz

85ns/66 MHz

010

2 (3 clocks)

75 (13.0ns)

44 (22.7ns)

011

3 (4 clocks)—default

80 (12.5ns)

66 (15.2ns)

100

4 (5 clocks)

Data[0]

High-Z

CLK

WAIT

DQ[15:0]

Data valid (or invalid) after one clock delay

D[0]

D[1]

D[2]

D[3]

D[4]

CLK

WAIT

DQ[15:0]

BCR[8] = 0

DATA VALID IN CURRENT CYCLE

BCR[8] = 1

DATA VALID IN NEXT CYCLE

Don't care

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