S71GS256 datasheet(120/195 Pages) SPANSION

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CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive

Strength

The output driver strength can be altered to full, one-half, or one-quarter

strength to adjust for different data bus loading scenarios. The reduced-strength

options are intended for stacked chip (Flash + CellularRAM) environments when

there is a dedicated memory bus. The reduced-drive-strength option minimizes

the noise generated on the data bus during READ operations. Normal output drive

strength should be selected when using a discrete CellularRAM device in a more

heavily loaded data bus environment. Outputs are configured at full drive

strength during testing.

WAIT Configuration (BCR[8]): Default = WAIT Transitions One

Clock Before Data Valid/Invalid

The WAIT configuration bit is used to determine when WAIT transitions between

the asserted and the de-asserted state with respect to valid data presented on

the data bus. The memory controller will use the WAIT signal to coordinate data

transfer during synchronous READ and WRITE operations. When BCR[8] = 0,

data will be valid or invalid on the clock edge immediately after WAIT transitions

to the de-asserted or asserted state, respectively (Figure 33 and Figure 35).

When A8 = 1, the WAIT signal transitions one clock period prior to the data bus

going valid or invalid (Figure 34).

WAIT Polarity (BCR[10]): Default = WAIT Active HIGH

The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH

or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-

down resistor to maintain the de-asserted state.

Table 20. Output Impedance

BCR[5]

BCR[4]

DRIVE STRENGTH

Full

1/2

1/4

Reserved

Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 35.

Figure 33. WAIT Configuration (BCR[8] = 0)

Data[0]

Data[1]

High-Z

CLK

WAIT

DQ[15:0]

Data immediately valid (or invalid)

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