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S71GS256 Datasheet(PDF) 157 Page - SPANSION |
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S71GS256 Datasheet(HTML) 157 Page - SPANSION |
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157 / 195 page  October 4, 2004 cellRAM_00_A0 CellularRAM Type 2 157 Ad vance Info rmat i o n Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. WAIT will assert LC + 1 or 2LC + 1 cycles for variable latency (depending upon refresh status). Figure 53. Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition Table 49. Burst WRITE Timing Parameters—BCR[8] = 0 Symbol 70ns/80 MHz 85ns/66 MHz Units MinMax MinMax tCLK 12.5 15 ns tHD 22 ns tKHTL 811 ns tSP 33 ns Don't Care Legend: VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# WAIT tCLK VIH VIL CLK (Note 2) VIH VIL OE# tOHZ VIH VIL WE# tKHTL tKHTL VOH VOL DQ[15:0] tHD tSP Valid Input D[n] Valid Input D[n+1] Valid Input D[n+3] Valid Input D[n+2] END OF ROW |
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