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S71GS256 Datasheet(PDF) 159 Page - SPANSION |
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S71GS256 Datasheet(HTML) 159 Page - SPANSION |
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159 / 195 page ![]() October 4, 2004 cellRAM_00_A0 CellularRAM Type 2 159 Ad vance Info rmat i o n tCSP 45 ns tHD 22 ns tKOH 22 ns tOHZ 88 ns tSP 33 ns Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. If CE# goes HIGH, it must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM). Figure 55. Asynchronous WRITE Followed by Burst READ Table 51. READ Timing Parameters—Burst WRITE Followed by Burst READ (Continued) Symbol 70ns/80 MHz 85ns/66 MHz Units MinMax MinMax tOHZ High-Z High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tCSP tSP tHD VIH VIL OE# WE# tSP tHD tCLK VIH VIL CLK tBOE Valid Address tWC tWC (Note 2) tWP tWPH tSP tHD Valid Output Valid Output Valid Output Valid Output VOH VOL tKOH tACLK High-Z Don't Care Undefined Legend: Valid Address Valid Address tCKA tSP tHD tBW tCW tAW tWR tCBPH tWC tCEW DATA tWHZ DATA tVPH tAVS tAVH tVP tVS tCVS tAS tDH tDW |
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