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S71GS256 Datasheet(PDF) 158 Page - SPANSION |
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S71GS256 Datasheet(HTML) 158 Page - SPANSION |
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158 / 195 page  158 CellularRAM Type 2 cellRAM_00_A0 October 4, 2004 Advan ce In form ati o n Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. To allow self-refresh operations to occur between transactions, CE# must remain HIGH for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. CE# can stay LOW between burst READ and burst WRITE operations. See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM). Figure 54. Burst WRITE Followed by Burst READ Table 50. WRITE Timing Parameters—Burst WRITE Followed by Burst READ Symbol 70ns/80 MHz 85ns/66 MHz Units Min Max Min Max tCBPH 55 ns tCLK 12.5 20 15 20 ns tCSP 4 20520 ns tHD 22 ns tSP 33 ns Table 51. READ Timing Parameters—Burst WRITE Followed by Burst READ Symbol 70ns/80 MHz 85ns/66 MHz Units MinMax MinMax tACLK 911 ns tBOE 20 20 ns tCLK 12.5 15 ns tOHZ High-Z High-Z tCBPH High-Z VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL A[22:0] ADV# CE# LB#/UB# DQ[15:0] WAIT tSP tCSP tSP tHD tHD VIH VIL OE# WE# tSP tHD tCLK VIH VIL CLK tHD tBOE Valid Address tSP tHD Valid Address tSP tHD (Note 2) tCSP tSP tHD tSP tHD D[0] D[3] D[2] D[1] Valid Output Valid Output Valid Output Valid Output VOH VOL tKOH tACLK tSP tHD High-Z Don't Care Undefined Legend: |
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