S71GS256 datasheet(167/195 Pages) SPANSION

167 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

167

Ad vance

Info rmat i o n

tWR

Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH

for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact Cel-

lularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).

Figure 59. Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW

Table 60. WRITE Timing Parameters—ADV# LOW

Symbol

70ns/80 MHz

85ns/66 MHz

Units

MinMax

tAS

tAW

tBW

tCW

Table 59. Asynchronous WRITE Timing Parameters Using ADV# (Continued)

Symbol

70ns/80 MHz

85ns/66 MHz

Units

MinMax

tOHZ

High-Z

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[22:0]

ADV#

CE#

LB#/UB#

DQ[15:0]

WAIT

tCEM

VIH

VIL

OE#

WE#

tBLZ

tOE

Valid

Address

(Note)

tWP tWPH

Valid

Output

VOH

VOL

tOLZ

Don't Care

Undefined

Legend:

Valid

Address

Valid

Address

tBW

tCW

tAW

tWR

tCBPH

tWC

DATA

tWHZ

DATA

tAS

tDH

tDW

tHZ

tBHZ

tAA

tHZ

tLZ

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