S71GS256 datasheet(169/195 Pages) SPANSION

169 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

169

Ad vance

Info rmat i o n

Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH

for at least 5ns (tCBPH) to schedule the appropriate internal refresh operation. See “How Extended Timings Impact Cel-

lularRAM™ Operation” for restrictions on the maximum CE# LOW time (tCEM).

Figure 60. Asynchronous WRITE Followed by Asynchronous READ

Table 62. WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ

Symbol

70ns/80 MHz

85ns/66 MHz

Units

MinMax

tAS

tAVH

tAVS

tAW

tBW

tCVS

tCW

tDH

tDW

tOHZ

High-Z

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

A[22:0]

ADV#

CE#

LB#/UB#

DQ[15:0]

WAIT

tCEM

VIH

VIL

OE#

WE#

tBLZ

tOLZ

Valid

Address

(Note)

tWP tWPH

Valid

Output

VOH

VOL

tOE

Don't Care

Undefined

Legend:

Valid

Address

Valid

Address

tBW

tCW

tAW

tWR

tCBPH

tWC

DATA

tWHZ

DATA

tAS

tDH

tDW

tBHZ

tAA

tHZ

tLZ

tAVS

tAVH

tVPH tVP

tVS

tCVS

tAS

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