S71GS256 datasheet(172/195 Pages) SPANSION

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172

CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

Page Mode READ Operation

When a CellularRAM device is configured for page mode operation, the address

inputs are used to accelerate read accesses and cannot be used by the on-chip

circuitry to schedule refresh. If CE# is LOW longer than the tCEM maximum time

of 4µs during a READ operation, the system must allow tAA (not tAPA, as would

otherwise be expected) for all subsequent intrapage accesses until CE# goes

HIGH.

Burst-Mode Operation

When configured for burst-mode operation, it is necessary to allow the device to

perform a refresh within any 4µs window. One of two conditions will enable the

device to schedule a refresh within 4µs. The first condition is when all burst op-

erations complete within 4µs. A burst completes when the CE# signal is

registered HIGH on a rising clock edge. The second condition that allows a refresh

is when a burst access crosses a row boundary. The row-boundary crossing

causes WAIT to be asserted while the next row is accessed and enables the

scheduling of refresh.

Summary

CellularRAM products are designed to ensure that any possible asynchronous tim-

ings do not cause data corruption due to lack of refresh. Slow bus timings on

asynchronous WRITE operations require that tWP and tDW be lengthened. Slow

bus timings during asynchronous page READ operations cause the next intrapage

READ data to be delayed to tAA.

Burst mode timings must allow the device to perform a refresh within any 4µs

period. A burst operation must either complete (CE# registered HIGH) or cross a

row boundary within 4µs to ensure successful refresh scheduling. These timing

requirements are likely to have little or no impact when interfacing a CellularRAM

device with a low-speed memory bus.

Figure 63. Extended WRITE Operation

tCEM or tTM > 4µs

tWP > tWC (MIN)

tDW > tWC (MIN)

ADDRESS

CE#

LB#/UB#

WE#

DATA-IN

S71GS256 Datasheet(PDF) 172 Page - SPANSION