S71GS256 datasheet(175/195 Pages) SPANSION

175 / 195 page

December 15, 2004 cellRAM_02_A0

CellularRAM-2A

175

Ad vance

Info rmat i o n

Notes:

1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only

DQ[7:0] are affected. When UB# only is in the select mode, DQ[15:8] are affected.

2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are

internally isolated from any external influence.

3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.

4. The device consumes active power in this mode whenever addresses are changed.

5. VIN = VCC or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.

6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.

VSSQ

Supply

VSSQ must be connected to ground.

Table 66. Bus Operations—Asynchronous Mode

Mode

Power

CE#

WE#

OE#

LB#/UB#

ZZ#

DQ[15:0]

(Note 1)Notes

Standby

High-Z

2, 5

Read

Active > Standby

Data-Out

1, 4

Write

Active > Standby

Data-In

1, 3, 4

Active

Standby

High-Z

4, 5

PAR

Partial Array Refresh

High-Z

DPD

Deep Power-down

High-Z

Load Configuration

Active

High-Z

Table 65. Pin Descriptions (Continued)

Symbol

Type

Description

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