S71GS256 datasheet(174/195 Pages) SPANSION

174 / 195 page

174

CellularRAM-2A

cellRAM_02_A0 December 15, 2004

Advan ce

In form ati o n

ation altogether and is used when no vital information is stored in the device.

These three refresh mechanisms are accessed through the CR.

Note: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing di-

agrams for detailed information.

Figure 64. Functional Block Diagram

Table 65. Pin Descriptions

Symbol

Type

Description

A[21:0]

Input

Address Inputs: Inputs for the address accessed during READ or WRITE operations. The

address lines are also used to define the value to be loaded into the configuration register.

ZZ#

Input

Sleep Enable: When ZZ# is LOW, the configuration register can be loaded or the device can

enter one of two low-power modes (DPD or PAR).

CE#

Input

Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and

goes into standby power mode.

OE#

Input

Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output

buffers are disabled.

WE#

Input

Write Enable: Enables WRITE operations when LOW.

LB#

Input

Lower Byte Enable. DQ[7:0]

UB#

Input

Upper Byte Enable. DQ[15:8]

DQ[15:0]

Input/

Output

Data Inputs/Outputs.

VCC

Supply

Device Power Supply: (1.7 V–1.95 V) Power supply for device core operation.

VCCQ

Supply

I/O Power Supply: (1.8 V) Power supply for input/output buffers.

VSS

Supply

VSS must be connected to ground.

A[21:0]

Input/

Output

MUX

and

Buffers

Control

Logic

4,096K x 16

DRAM

Memory

Array

CE#

WE#

OE#

LB#

UB#

DQ[7:0]

DQ[15:8]

Address Decode

Logic

Configuration

ZZ#

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