S71GS256 datasheet(173/195 Pages) SPANSION

173 / 195 page

December 15, 2004 cellRAM_02_A0

CellularRAM-2A

173

Ad vance

Info rmat i o n

CellularRAM-2A

64 Megabit

Asynchronous CellularRAM

Features

Asynchronous and Page Mode interface

Random Access Time: 70 ns

Page Mode Read Access

— Sixteen-word page size

— Interpage read access: 70 ns

— Intrapage read access: 20 ns

VCC, VCCQ Voltages

— 1.70 V to 1.95 V VCC

— 1.70 V to 2.25 V VCCQ

Low Power Consumption

— Asynchronous READ < 25 mA

— Intrapage READ < 15 mA

— Standby: 100 µA

— Deep power-down < 10 µA

Low-Power Features

— Temperature Compensated Refresh (TCR)

— Partial Array Refresh (PAR)

— Deep Power-Down (DPD) Mode

General Description

CellularRAM™ products are high-speed, CMOS dynamic random access memories

that have been developed for low-power portable applications. The 64Mb device

is organized as 4 Meg x 16 bits. These devices include the industry-standard,

asynchronous memory interface found on other low-power SRAM or Pseudo

SRAM offerings.

A user-accessible configuration register (CR) has been included to define device

operation. The CR defines how the CellularRAM device performs on-chip refresh

and whether page mode read accesses are permitted. This register is automati-

cally loaded with a default setting during power-up and can be updated at any

time during normal operation.

To operate smoothly on an asynchronous memory bus, CellularRAM products

have incorporated a transparent self refresh mechanism. The hidden refresh re-

quires no additional support from the system memory controller and has no

significant impact on device read/write performance.

Special attention has been focused on current consumption during self refresh.

CellularRAM products include three system-accessible mechanisms used to min-

imize refresh current. Temperature compensated refresh (TCR) is used to adjust

the refresh rate according to the case temperature. The refresh rate can be de-

creased at lower temperatures to minimize current consumption during standby.

Setting the sleep enable pin ZZ# to LOW enables one of two low-power modes:

partial array refresh (PAR); or deep power-down (DPD). PAR limits refresh to only

that part of the DRAM array that contains essential data. DPD halts refresh oper-

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