S71GS256 datasheet(176/195 Pages) SPANSION

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CellularRAM-2A

cellRAM_02_A0 December 15, 2004

Advan ce

In form ati o n

Functional Description

The 64Mb async/page CellularRAM device is a high-density alternative to SRAM

and Pseudo SRAM products, popular in low-power, portable applications. The de-

vice contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. It

includes the industry-standard, asynchronous memory interface found on other

low-power SRAM or Pseudo SRAM offerings. Page mode accesses are also in-

cluded as a bandwidth-enhancing extension to the asynchronous read protocol.

Power-Up Initialization

CellularRAM products include an on-chip voltage sensor that is used to launch the

power-up initialization process. Initialization will load the CR with its default set-

tings. VCC and VCCQ must be applied simultaneously, and when they reach a

stable level above 1.70 V, the device requires 150 µs to complete its self initial-

ization process (see Figure 2). During the initialization period, CE# should remain

HIGH. When initialization is complete, the device is ready for normal operation.

At power-up, the CR is set to 0070h.

Bus Operating Modes

CellularRAM products incorporate the industry-standard, asynchronous interface

found on other low-power SRAM or Pseudo SRAM offerings. This bus interface

supports asynchronous READ and WRITE operations as well as the bandwidth-

enhancing page mode READ operation. The specific interface that is supported is

defined by the value loaded into the CR.

Asynchronous Mode

CellularRAM products power up in the asynchronous operating mode. This mode

uses the industry standard SRAM control interface (CE#, OE#, WE#, LB#/ UB#).

READ operations (Figure 66) are initiated by bringing CE#, OE#, and LB#/UB#

LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the

specified access time has elapsed. WRITE operations (Figure 67) occur when

CE#, WE#, and LB#/ UB# are driven LOW. During WRITE operations, the level

of OE# is a “Don't Care”; WE# will override OE#. The data to be written will be

latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first).

Figure 65. Power-Up Initialization Timing

VCC

VCCQ

tPU > 150 µs

Device Initialization

Device ready for

normal operation

VCC = 1.7 V

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