S71GS256 datasheet(179/195 Pages) SPANSION

179 / 195 page

December 15, 2004 cellRAM_02_A0

CellularRAM-2A

179

Ad vance

Info rmat i o n

frequent refresh operations to maintain data integrity as temperatures increase.

More frequent refresh is required due to the increased leakage of the DRAM's ca-

pacitive storage elements as temperatures rise. A decreased refresh rate at lower

temperatures will facilitate a savings in standby current.

TCR allows for adequate refresh at four different temperature thresholds: +15°C,

+45°C, +70°C, and +85°C. The setting selected must be for a temperature

higher than the case temperature of the CellularRAM device. If the case temper-

ature is +50°C, the system can minimize self refresh current consumption by

selecting the +70°C setting. The +15°C and +45°C settings would result in inad-

equate refreshing and cause data corruption.

Partial Array Refresh

Partial array refresh (PAR) restricts refresh operation to a portion of the total

memory array. This feature enables the system to reduce refresh current by only

refreshing that part of the memory array that is absolutely necessary. The refresh

options are full array, three-quarters array, one-half array, one-quarter array, or

none of the array. Data stored in addresses not receiving refresh will become cor-

rupted. The mapping of these partitions can start at either the beginning or the

end of the address map (Tables 5 and 6). READ and WRITE operations are ignored

during PAR operation.

The device can only enter PAR mode if the SLEEP bit in the configuration register

has been set HIGH (CR[4] = 1). PAR is initiated by bring the ZZ# pin to the LOW

state for longer than 10µs. Returning ZZ# to HIGH will cause an exit from PAR

and the entire array will be immediately available for READ and WRITE

operations.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode

is used when the system does not require the storage provided by the Cellular-

RAM device. Any stored data will become corrupted when DPD is entered. When

refresh activity has been re-enabled, the CellularRAM device will require 150µs

to perform an initialization procedure before normal operations can resume.

READ and WRITE operations are ignored during DPD operation.

The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4]

= 0). DPD is initiated by bringing the ZZ# pin to the LOW state for longer than

10µs. Returning ZZ# to HIGH will cause the device to exit DPD and begin a 150µs

initialization process. During this 150µs period, the current consumption will be

higher than the specified standby levels but considerably lower than the active

current specification.

Driving the ZZ# pin LOW will place the device in the PAR mode if the SLEEP bit

in the CR has been set HIGH (CR[4] = 1).

Configuration Register Operation

The configuration register (CR) defines how the CellularRAM device performs its

transparent self refresh. This register is automatically loaded with default settings

during power-up and can be updated anytime while the device is operating in a

standby state.

The CR is loaded using a WRITE operation immediately after ZZ# makes a HIGH-

to-LOW transition (Figure 69). The values placed on addresses A[21:0] are

latched into the CR on the rising edge of CE# or WE#, whichever occurs first. Al-

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