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S71GS256 Datasheet(PDF) 181 Page - SPANSION |
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S71GS256 Datasheet(HTML) 181 Page - SPANSION |
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181 / 195 page ![]() December 15, 2004 cellRAM_02_A0 CellularRAM-2A 181 Ad vance Info rmat i o n Table 67. Configuration Register Bit Mapping Table 68. 64Mb Address Patterns for PAR (CR[4] = 1) CR[2] CR[1] CR[0] Active Section Address Space Size Density 0 0 0 Full die 000000h–3FFFFFh 4 Meg x 16 64Mb 0 0 1 Three-quarters of die 000000h–2FFFFFh 3 Meg x 16 48Mb 0 1 0 One-half of die 000000h–1FFFFFh 2 Meg x 16 32Mb 0 1 1 One-quarter of die 000000h–0FFFFFh 1 Meg x 16 16Mb 1 0 0 None of die 0 0 Meg x 16 0Mb 1 0 1 Three-quarters of die 100000h–3FFFFFh 3 Meg x 16 48Mb 1 1 0 One-half of die 200000h–3FFFFFh 2 Meg x 16 32Mb 1 1 1 One-quarter of die 300000h–3FFFFFh 1 Meg x 16 16Mb PAR A4 A3 A2 A1 A0 Configuration Register Address Bus 4 1 2 3 0 RESERVED 6 5 A5 0 1 Sleep Mode DPD Enabled PAR Enabled (default) CR[4] TCR CR[6] CR[5] 11 1 1 00 0 0 Maximum Case Temp. +85 C (default) +70 C +45 C +15 C A6 21– 8 RESERVED A[21:8] CR[1] 0 0 1 1 CR[0] 0 1 0 1 PAR Refresh Coverage Full array (default) Bottom 3/4 array Bottom 1/2 array Bottom 1/4 array CR[2] 0 0 0 0 00 1 01 1 1 0 1 11 1 None of array Top 3/4 array Top 1/2 array Top 1/4 array SLEEP Must be set to "0" All must be set to "0" A7 7 PAGE 0 1 Page Mode Enable/Disable Page Mode Disabled (default) Page Mode Enabled CR[7] |
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