S71GS256 datasheet(185/195 Pages) SPANSION

185 / 195 page

December 15, 2004 cellRAM_02_A0

CellularRAM-2A

185

Ad vance

Info rmat i o n

Notes:

1. High-Z to Low-Z timings are tested with the circuit shown in Figure 71 on page 184. The Low-Z timings measure a

100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 71 on page 184. The High-Z timings measure

a 100mV transition from either VOH or VOL toward VCCQ/2.

Table 75. READ Cycle Timing Requirements

Parameter

Symbol

Min

Max

Units

Notes

Address Access Time

tAA

Page Access Time

tAPA

LB#/UB# Access Time

tBA

LB#/UB# Disable to High-Z Output

tBHZ

LB#/UB# Enable to Low-Z Output

tBLZ

Chip Select Access Time

tCO

Chip Disable to High-Z Output

tHZ

Chip Enable to Low-Z Output

tLZ

Output Enable to Valid Output

tOE

Output Hold from Address Change

tOH

5ns

Output Disable to High-Z Output

tOHZ

Output Enable to Low-Z Output

tOLZ

5ns

Page Cycle Time

tPC

READ Cycle Time

tRC

S71GS256 Datasheet(PDF) 185 Page - SPANSION

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