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S71GS256 Datasheet(PDF) 186 Page - SPANSION |
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S71GS256 Datasheet(HTML) 186 Page - SPANSION |
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186 / 195 page  186 CellularRAM-2A cellRAM_02_A0 December 15, 2004 Advan ce In form ati o n Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 71 on page 184. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 71 on page 184. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. Table 76. WRITE Cycle Timing Requirements Parameter Symbol Min Max Units Notes Address Setup Time tAS 0ns Address Valid to End of Write tAW 70 ns Byte Select to End of Write tBW 70 ns CE# HIGH Time During Write tCEH 5ns Maximum CE# Pulse Width tCEM 10 µs Chip Enable to End of Write tCW 70 ns Data Hold from Write Time tDH 0ns Data WRITE Setup Time tDW 23 ns Chip Enable to Low-Z Output tLZ 10 ns 1 End WRITE to Low-Z Output tOW 5ns Write Cycle Time tWC 70 ns Write to High-Z Output tWHZ 08 ns 2 Write Pulse Width tWP 46 Write Recovery Time tWR 0ns Table 77. Load Configuration Register Timing Requirements Parameter Symbol Min Max Units Notes Address Setup Time tAS 0ns Address Valid to End of Write tAW 70 ns Chip Deselect to ZZ# LOW tCDZZ 5ns Chip Enable to End of Write tCW 70 ns Write Cycle Time tWC 70 ns Write Pulse Width tWP 40 ns Write Recovery Time tWR 0ns ZZ# LOW to WE# LOW tZZWE 10 ns Table 78. Deep Power Down Timing Requirements Parameter Symbol Min Max Units Notes Chip Deselect to ZZ# LOW tCDZZ 5ns Deep Power-Down Recovery tR 150 µs Minimum ZZ# Pulse Width tZZMIN 10 µs |
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