S71GS256 datasheet(184/195 Pages) SPANSION

184 / 195 page

184

CellularRAM-2A

cellRAM_02_A0 December 15, 2004

Advan ce

In form ati o n

Table 71. Partial Array Refresh Specifications and Conditions

Note:IPAR (MAX) values measured with TCR set to 85°C.

Notes:

1. These parameters are verified in device characterization and are not 100% tested.

AC Characteristics

Description

Conditions

Symbol

Density

Array

Partition

Typ

Max

Units

Partially Array Refresh Current

VIN = VCCQ or 0V,

ZZ# = Low

CR[4] = 1

IPAR

64 Mb

Full

100

µA

3/4

TBD

1/2

TBD

1/4

TBD

050

Table 72. Deep Power-Down Specifications

Description

Conditions

Symbol

Typ

Max

Units

Deep Power-down

VIN = VCCQ or 0V; +25°C; ZZ# = LOW CR[4] = 0

IZZ

µA

Table 73. Capacitance Specifications and Conditions

Description

Conditions

Symbol

Min

Max

Units

Notes

Input Capacitance

TC = +25ºC; f = 1 MHz; VIN = 0V

CIN

-6

Input/Output Capacitance (DQ)

CIO

-6

Notes:

1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and output

timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 1.6ns.

Figure 70. AC Input/Output Reference Waveform

Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).

Figure 71. Output Load Circuit

Table 74. Output Load Circuit

VCCQR1/R2

1.8 V

2.7 KΩ

Output

Test Points

Input

VCCQ

VSS

VCCQ/2

DUT

VCCQ

30pF

Test Point

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