S71GS256 datasheet(193/195 Pages) SPANSION

193 / 195 page

December 15, 2004 cellRAM_02_A0

CellularRAM-2A

193

Ad vance

Info rmat i o n

How Extended Timings Impact CellularRAM™ Operation

Introduction

CellularRAM products use a DRAM technology that periodically requires refresh to

ensure against data corruption. CellularRAM devices include on-chip circuitry that

performs the required refresh in a manner that is completely transparent in sys-

tems with normal bus timings. The refresh circuitry does impose constraints on

timings in systems that take longer than 10µs to complete WRITE operations.

This section describes CellularRAM timing requirements in systems that perform

extended operations.

Operation When Page Mode is Disabled

CellularRAM products require that all WRITE operations must be completed within

10µs. After completing an operation, the device must either enter standby (by

transitioning CE# HIGH), or else perform a second operation using a new ad-

dress. Figures 80 and 81 demonstrate these constraints as they apply during an

asynchronous (page-mode-disabled) operation. Either the CE# active period

(tCEM in Figure 80) or the address valid period (tTM in Figure 81) must be less than

10 µs during any operation to accommodate orderly scheduling of refresh.

Note:Timing constraints when page mode is enabled.

Figure 80. Extended Timing for tCEM

Note:Timing constraints when page mode is enabled.

Figure 81. Extended Timing for tTM

Operation When Page Mode is Enabled

When a CellularRAM device is configured for page mode operation, the address

inputs are used to accelerate read accesses and cannot be used by the on-chip

circuitry to schedule refresh. CE# must return HIGH upon completion of all

WRITE operations when page mode is enabled (Figure 82). The total time taken

for a WRITE operation should not exceed 10 µs to accommodate orderly sched-

uling of refresh.

CE#

ADDRESS

tCEM

10 µs

CE#

ADDRESS

TM<

10µs

S71GS256 Datasheet(PDF) 193 Page - SPANSION