S71GS256 datasheet(194/195 Pages) SPANSION

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194

CellularRAM-2A

cellRAM_02_A0 December 15, 2004

Advan ce

In form ati o n

Note:Timing constraints when page mode is enabled.

Figure 82. Extended Timing for tCEM (2)

Impact on Extended WRITE Operations

Modified timings are only required during extended WRITE operations (see Figure

83 below). An extended WRITE operation requires that both the write pulse width

(tWP) and the data valid period (tDW) will need to be lengthened to at least the

minimum WRITE cycle time (tWC[MIN]). These increased timings ensure that time

is available for both a refresh operation and successful completion of the WRITE

operation.

Summary

CellularRAM products are designed to ensure that any possible bus timings do not

cause corruption of array data due to lack of refresh. The on-chip refresh circuitry

will only affect the required timings for WRITE operations (READs are unaffected)

performed in a system with a slow memory interface. The impact for WRITE op-

erations is that some of the timing parameters (tWP, tDW) are lengthened. The

modified timings are likely to have little or no impact when interfacing a Cellular-

RAM device with a low-speed memory bus.

Figure 83. Extended WRITE Operation

CE#

tCEM 10µs

tCEM or tTM > 4µs

tWP > tWC (MIN)

tDW > tWC (MIN)

ADDRESS

CE#

LB#/UB#

WE#

DATA-IN

S71GS256 Datasheet(PDF) 194 Page - SPANSION