MC68340 datasheet(367/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

8- 23

Disabled—TOUTx is disabled and three-stated.

Toggle Mode—If the timer is disabled (SWR = 0) when this encoding is programmed,

TOUTx is immediately set to zero. If the timer is enabled (SWR = 1), timeout events

(counter reaches $0000) toggle TOUTx. In the input capture/output compare mode,

TOUTx is immediately set to zero if the timer is disabled (SWR = 0). If the timer is

enabled (SWR = 1), timer compare events toggle TOUTx. (Timer compare events occur

when the counter reaches the value stored in the COM.)

Zero Mode—If the timer is disabled (SWR = 0) when this encoding is programmed,

TOUTx is immediately set to zero. If the timer is enabled (SWR = 1), TOUTx will be set

to zero at the next timeout. In the input capture/output compare mode, TOUTx is

immediately set to zero if the timer is disabled (SWR = 0). If the timer is enabled (SWR

= 1), TOUTx will be set to zero at timeouts and set to one at timer compare events. If

the COM is $0000, TOUTx will be set to zero at the timeout/timer compare event.

One Mode—If the timer is disabled (SWR = 0) when this encoding is programmed,

TOUTx is immediately set to one. If the timer is enabled (SWR = 1), TOUTx will be set

to one at the next timeout. In the input capture/output compare mode, TOUTx is

immediately set to one if the timer is disabled (SWR = 0). If the timer is enabled (SWR =

1), TOUTx will be set to one at timeouts and set to zero at timer compare events. If the

COM is $0000, TOUTx will be set to one at the timeout/timer compare event.

8.4.4 Status Register (SR)

The SR contains timer status information as well as the state of the prescaler. This

in progress, allowing the most current information to be contained in this register. The

enabled (i.e., the STP bit in the MCR is cleared).

$608, $648

9876543210

IRQ

TGL

OUT

COM

PO7

PO6

PO5

PO4

PO3

PO2

PO1

PO0

RESET (

TGATE

≈ NEGATED):

0000100011111111

RESET (

TGATE

≈ ASSERTED):

0000000011111111

Supervisor/User

IRQ—Interrupt Request bit

The positioning of this bit in the most significant location in this register allows it it be

conditionally tested as if it were a signed binary integer.

1 = An interrupt condition has occurred. This bit is the logical OR of the enabled TO,

TG, and TC interrupt bits.

0 = The bit(s) that caused the interrupt condition has been cleared. If an

IRQ

≈ signal

has been asserted, it is negated when this bit is cleared.

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