MC68340 datasheet(369/441 Pages) FREESCALE

369 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

8- 25

1 = This bit is set when the counter output equals the value in the COM.

0 = This bit is cleared when a timeout occurs, the COM register is accessed (read or

write), the timer is reset with the SWR bit, or the

RESET signal is asserted on the

IMB. This bit is cleared regardless of the state of the TC bit.

This bit can be used to indicate when a write to the PREL1 or PREL2 registers will not

cause a problem during a counter reload at timeout. To ensure that the write to the

PREL register is recognized at timeout, the latency between the read of the COM bit

and the write to the PREL register must be considered.

PO7–PO0—Prescaler Output

These bits show the levels on each of the eight output taps of the prescaler. These

values are updated every time that the system clock goes high and a read cycle of this

byte in the SR is not in progress.

8.4.5 Counter Register (CNTR)

The CNTR reflects the value of the counter. This value can be reliably read at any time

since it is updated on every rising edge of the system clock (except in the input

capture/output compare mode) when a read of the register is not in progress. This read-

only register can be read when the timer module is enabled (i.e. the STP bit in the MCR is

cleared).

CNTR

$60A, $64A

9876543210

CNT15

CNT14

CNT13

CNT12

CNT11

CNT10

CNT9

CNT8

CNT7

CNT6

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

RESET:

0000000000000000

Supervisor/User

All 24 bits of the prescaler and the counter may be obtained by one long-word read at the

address of the SR, since the CNTR is contiguous to it. Any changes in the prescaler value

due to the two cycles necessary to perform a long-word read should be considered. If this

latency presents a problem, the

TGATE

≈ signal may be used to disable the decrement

function while the reads are occurring.

8.4.6 Preload 1 Register (PREL1)

The PREL1 stores a value that is loaded into the counter in some modes of operation.

This value is loaded into the counter on the first falling edge of the counter clock after the

counter is enabled. This register can be be read and written when the timer module is

enabled (i.e. the STP bit in the MCR is cleared). However, a write to this register must be

completed before timeout for the new value to be reliably loaded into the counter.

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