AD5934 datasheet(12/32 Pages) AD

12 / 32 page

AD5934

Rev. 0 | Page 12 of 32

TRANSMIT STAGE

As shown in Figure 16, the transmit stage of the AD5934 is made

up of a 27-bit phase accumulator DDS core which provides the

output excitation signal at a particular frequency. The input to the

phase accumulator is taken from the contents of the START

FREQUENCY register (see RAM Locations 82h, 83h, and 84h).

Although the phase accumulator offers 27 bits of resolution, the

START FREQUENCY register has the 3 most significant bits

(MSBs) set to 0 internally; therefore the user has the ability to

program only the lower 24 bits of the START FREQUENCY

The AD5934 offers a frequency resolution programmable by the

user down to 0.1 Hz. The frequency resolution is programmed via

a 24-bit word loaded serially over the I2C interface to the

FREQUENCY INCREMENT register.

The frequency sweep is fully described by the programming of

three parameters: the START FREQUENCY, the FREQUENCY

INCREMENT, and the NUMBER OF INCREMENTS.

START FREQUENCY

This is a 24-bit word that is programmed to the on-board RAM at

Address 82h, Address 83h, and Address 84h (see the Register Map

section). The required code loaded to the START FREQUENCY

the master clock frequency and the required start frequency

output from the DDS.

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛ MCLK

Frequency

Start

Output

Required

Code

Frequency

Start

(1)

For example, if the user requires the sweep to begin at 30 kHz and

has a 16 MHz clock signal connected to MCLK. The code that

needs to be programmed is given by

hexidecima

3D70A3

MHz

kHz

≡

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

Code

Frequency

Start

The user programs 3D hex to Register 82 h, 70 hex to

FREQUENCY INCREMENT

This is a 24-bit word that is programmed to the on-board

RAM at Address 85 h, Address 86 h, and Address 87 h (see

the Register Map section). The required code loaded to the

frequency increment register is the result of the formula shown in

Equation 2, based on the master clock frequency and the required

increment frequency output from the DDS.

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛ MCLK

Increment

Frequency

Required

Code

Increment

Frequency

(2)

For example, if the user requires the sweep to have a resolution of

10 Hz and has a 16 MHz clock signal connected to MCLK, the

code that needs to be programmed is given by

hexidecima

00053E

MHz

≡

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

Code

Increment

Frequency

The user programs 00 hex to Register 85 h, 05 hex to

NUMBER OF INCREMENTS

This is a 9-bit word that represents the number of frequency

points in the sweep. The number is programmed to the on-board

RAM at Address 88 h and Address 89 h (see the Register Map

section). The maximum number of points that can be

programmed is 511.

For example, if the sweep needs 150 points, the user programs

00 hex to Register 88 h and 96 hex to Register 89 h.

Once the three parameter values have been programmed, the

sweep is initiated by issuing a Start Frequency Sweep command

to the CONTROL register at Address 80 h and Address 81 h

(see the Register Map section). Bit 2 in the STATUS register

(Register 8F h) indicates the completion of the frequency

measurement for each sweep point. Incrementing to the next

frequency sweep point is under the control of the user. The

measured result is stored in two registers (94 h, 95 h and 96 h,

97 h) which should be read before issuing an Increment

Frequency command to the CONTROL register to move to the

next sweep point. There is the facility to repeat the current

frequency point measurement by issuing a Repeat Frequency

command to the CONTROL register. This has the benefit of

allowing the user to average successive readings. When the

frequency sweep has completed all frequency points, Bit 3 in the

STATUS register is set, indicating completion of the sweep. Once

this bit is set further increments are disabled.

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