AD7765 datasheet(13/21 Pages) AD

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Preliminary Technical Data

AD7765

Rev. PrC | Page 13 of 21

AD7765 INTERFACE

READING DATA

The AD7765 uses an SPI compatible serial interface. The timing

diagram in Figure 2 shows how the AD7765 transmits its

conversion results.

The data being read from the AD7765 is clocked out using the

serial clock output, SCO. The SCO frequency is half that of the

MCLK input to the AD7765.

The conversion result output on the serial data output (SDO)

line is framed by the frame synchronization output, FSO, which

is sent logic low for 32 SCO cycles. Each bit of the new

conversion result is clocked onto the SDO line on the rising

SCO edge and is valid on the falling SCO edge. The 32-bit result

consists of the 24 data bits which, are followed by 5 status bits

followed by a further 3 zeros. The five status bits are :

DVALID

OVR

LPWR

Dec_Rate 1

Dec_Rate 0

WRITING TO THE AD7765

The AD7765 write operation is shown in Figure 3. The serial

writing operation is synchronous to the SCO signal. The status

of the frame sync input,FSI , is checked on the falling edge of

the SCO signal. If the FSI line is low then the first data bit on

the serial data in (SDI) line is latched in on the next SCO falling

edge.

The active edge of the FSI signal should be set to occur at a

position when the SCO signal is high or low, which allows set-

up and hold time from the SCO falling edge to be met. The

width of the FSI signal may be set to between 1 and 32 SCO

periods wide. A second or subsequent FSI falling edge which

occurs before 32 SCO periods have elapsed will be ignored.

Figure 3 details the format for the serial data being written to

the AD7765, through the SDI pin. 32 bits are required for a

write operation. The first 16 bits are used to select the register

address that the data being read is intended for. The second 16

bits contain the data for the selected register.

Writing to AD7765 should be allowed at any time even while

reading a conversion result. It should be noted that after writing

to the devices, valid data will not be output until after the

settling time for the filter has elapsed. The DVALID status bit is

asserted at this point to indicate that the filter has settled and

that valid data is available at the output.

READING STATUS AND OTHER REGISTERS

The AD7765 features a programmable control registers and a

read-only status register. To read back the contents of these

registers, the user must first write to the control register of the

device, setting a bit corresponding to the register to be read.

The next read operation then outputs the contents of the

selected register instead of a conversion result.

To ensure that the next read cycle contains the contents of the

in question must be completed a minimum of 8 × tSCO before

the falling edge of FSO, which indicates the start of the next

read cycle. See Figure 4 for details.

Information on the relevant bits that must be set in the control

SYNCHRONISATION

The SYNC input to the AD7765 provides a synchronization

function that allows the user to begin gathering samples of the

analog front-end input from a known point in time.

The SYNC function allows multiple AD7765s, operated from

the same master clock and using the same SYNC signal, to be

synchronized so that each ADC simultaneously updates its

output register.

Using a common SYNC signal to all AD7765 devices in a

system allows synchronization to occur. On the falling edge of

the SYNC signal the digital filter sequencer is reset to 0. The

filter is held in reset state until a rising edge of the SCO senses

SYNC high. Thus, to perform a synchronization of devices, a

SYNC pulse of a minimum of 2.5 ICLK cycles in length can be

applied, synchronous to the falling edge of SCO. On the first

rising edge of SCO after SYNC goes logic high, the filter is taken

out of reset, and the multiple parts gather input samples

synchronously.

Following a SYNC, the digital filter needs time to settle before

valid data can be read from the AD7765. The user knows there

is valid data on the SDO line by checking the DVALID status bit

(see D7 in the status bits listing) that is output with each conversion

result. The time from the rising edge of SYNC until the DVALID

bit is asserted is dependent on the filter configuration used. See the

Theory of Operation section and the figures listed in Table 5 for

details on calculating the time until DVALID is asserted.

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