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AD7765

Preliminary Technical Data

Rev. PrC | Page 16 of 21

CLOCKING THE AD7765

The AD7765 requires an external low jitter clock source. This

signal is applied to the MCLK pin. An internal clock signal

(ICLK) is derived from the MCLK input signal. This ICLK

controls all the internal operation of the AD7765. The

maximum ICLK frequency is

20MHz. The ICLK is generated

as follows:

ICLK = MCLK/2

If the user wishes to get output data rates equal to those used in

audio systems, a

12.288 MHz ICLK frequency can be used. As

shown in Table 5, output data rates of 96kHz and 48kHz are

achievable with this ICLK frequency.

The MCLK jitter requirements depend on a number of factors

and are given by the following equation:

)

(

)

(

SNR

RMS

OSR

Where:

OSR = Over-sampling ratio =

ODR

ICLK

fIN

= Maximum Input Frequency

SNR(dB) = Target SNR.

EXAMPLE 1

This example can be taken from Table 5, where:

ODR = 156.25 kHz

fICLK = 20MHz

fIN (max) = 78.125 kHz

SNR = 109dB

RMS

125

128

)

(

This is the maximum allowable clock jitter for a full-scale

78.125kHz input tone with the given ICLK and Output Data

Rate.

EXAMPLE 2

Taking a second example from Table 5, where:

ODR = 48kHz

fICLK

= 12.288MHz

fIN

(max) = 19.2kHz

SNR = 112dB

RMS

333

256

)

(

The input amplitude also has an effect on these jitter figures. If,

for example, the input level was 3dB down from full-scale , the

allowable jitter would be increased by a factor of √2 increasing

the figure calculated in the first example from 81.77ps to

115.64ps RMS. This is because the maximum slew rate is

reduced by a reduction in amplitude. Figure 18 and Figure 19

illustrate this point showing the maximum slew rate of a sine

wave of the same frequency but with different amplitudes.

Figure 18. Maximum Slew Rate of Sine Wave with Amplitude of 2V Pk-Pk

Figure 19. Maximum Slew Rate of Same Frequency Sine Wave with

Amplitude of 1V Pk-Pk

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