P87LPC778FDH datasheet(33/79 Pages) PHILIPS

33 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

33 of 79

9397 750 12378

Table 31 summarizes the interrupt sources, ﬂag bits, vector addresses, enable bits,

priority bits, arbitration ranking, and whether each interrupt may wake up the CPU

from Power-down mode.

8.8.1

External interrupt inputs

The P87LPC778 has two individual interrupt inputs as well as the Keyboard Interrupt

function. The latter is described separately elsewhere in this section. The two

interrupt inputs are identical to those present on the standard 80C51 microcontroller.

The external sources can be programmed to be level-activated or transition-activated

by setting or clearing bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is

triggered by a detected low at the INTn pin. If ITn = 1, external interrupt n is edge

triggered. In this mode if successive samples of the INTn pin show a high in one cycle

and a low in the next cycle, interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

Since the external interrupt pins are sampled once each machine cycle, an input high

or low should hold for at least 6 CPU Clocks to ensure proper sampling. If the

external interrupt is transition-activated, the external source has to hold the request

pin high for at least one machine cycle, and then hold it low for at least one machine

cycle. This is to ensure that the transition is seen and that interrupt request ﬂag IEn is

set. IEn is automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-activated, the external source must hold the request

active until the requested interrupt is actually generated. If the external interrupt is still

asserted when the interrupt service routine is completed another interrupt will be

generated. It is not necessary to clear the interrupt ﬂag IEn when the interrupt is level

sensitive, it simply tracks the input pin level.

If an external interrupt is enabled when the P87LPC778 is put into Power-down or

Idle mode, the interrupt will cause the processor to wake up and resume operation.

Refer to Section 8.12 “Power reduction modes” on page 43 for details.

Table 31:

Summary of interrupts

Description

Interrupt

Flag Bit(s)

Vector

Address

Interrupt

Enable Bit(s)

Interrupt

Priority

Arbitration

Ranking

Power-down

Wake-up

External Interrupt 0

IE0

0003h

EX0 (IEN0.0)

IP0H.0, IP0.0

1 (highest)

Yes

Timer0 Interrupt

TF0

000Bh

ET0 (IEN0.1)

IP0H.1, IP0.1

External Interrupt 1

IE1

0013h

EX1 (IEN0.2)

IP0H.2, IP0.2

Yes

Timer1 Interrupt

TF1

001Bh

ET1 (IEN0.3)

IP0H.3, IP0.3

Serial Port Tx and Rx

TI & RI

0023h

ES (IEN0.4)

IP0H.4, IP0.4

Brownout Detect

BOD

002Bh

EBO (IEN0.5)

IP0H.5, IP0.5

Yes

I2C-bus Interrupt

ATN

0033h

EI2 (IEN1.0)

IP1H.0, IP1.0

KBI Interrupt

KBF

003Bh

EKB (IEN1.1)

IP1H.1, IP1.1

Yes

Comparator 2 interrupt

CMF2

0043h

EC2 (IEN1.2)

IP1H.2, IP1.2

Yes

Watchdog Timer

WDOVF

0053h

EWD (IEN0.6)

IP0H.6, IP0.6

Yes

A/D Converter

ADCI

005Bh

EAD (IEN1.4)

IP1H.4, IP1.4

Yes

Comparator 1 interrupt

CMF1

0063h

EC1 (IEN1.5)

IP1H.5, IP1.5

Yes

Timer I interrupt

0073h

ETI (IEN1.7)

IP1H.7, IP1.7

13 (lowest)

P87LPC778FDH Datasheet(PDF) 33 Page - NXP Semiconductors

P87LPC778FDH Datasheet(HTML) 33 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL