P87LPC778FDH datasheet(24/79 Pages) PHILIPS

24 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

24 of 79

9397 750 12378

If PWMCON1 is written with Transfer set without Run being enabled the transfer will

never take place.

If a subsequent write sets Run without Transfer the compare and counter values will

not be updated.

If Transfer and Run are set, and prior to underﬂow there is a subsequent load of

PWMCON0 which sets Run but not Transfer, the transfer will never take place. The

compare and counter values that existed prior to the update attempt will be used.

As outlined above the Transfer bit can be polled to determine when the transfer

occurs. Unless there is a compelling reason to do otherwise, it is recommended that

both Run, PWMCON0.7, and Transfer, PWMCON0.6, be set when PWMCON0 is

written. When the Run bit, PWMCON0.7, is cleared the PWM outputs take on the

state they had just prior to the bit being cleared. In general this state is not known.

In order to place the outputs in a known state when Run is cleared the Compare

registers can be written to either the ‘always 1’ or ‘always 0’ so the output will have

the output desired when the counter is halted. After this PWMCON0 should be written

with the Transfer and Run bits are enabled. After this is done PWMCON0 is polled to

ﬁnd that the Transfer has taken place. Once the transfer has occurred the Run bit in

PWMCON0 can be cleared. The outputs will retain the state they had just prior to the

Run being cleared.

Table 18:

PWMCON0 - PWM control register 0 (address 0DAH) bit allocation

Reset value: 00H

Bit

Symbol

RUN

XFER

PWM3I

PWM2I

PWM1I

PWM0I

Table 19:

PWMCON0 - PWM control register 0 (address 0DAH) bit description

Bit

Symbol

Value

Description

RUN

Counter halted and preset value loaded. If Brake is

asserted, PWMx output will be equal to the value of the

corresponding PWMxB bit (PWMCON1[3:0]). If Brake is

not asserted, PWMx output will be equal to the Value after

compare.

Counter run

XFER

Counter run

Counter and compare shadow registers are not

connected to the active registers

PWM3I

PWM3 output is non-inverted. Output is a ‘1’ from the start

of the cycle until compare; ‘0’ thereafter.

PWM3 output is inverted. Output is a ‘0’ from the start of

the cycle until compare; ‘0’ thereafter.

PWM2I

PWM2 output is non-inverted. Output is a ‘1’ from the start

of the cycle until compare; ‘0’ thereafter.

PWM2 output is inverted. Output is ‘0’ from the start of the

cycle until compare; ‘1’ thereafter.

P87LPC778FDH Datasheet(PDF) 24 Page - NXP Semiconductors

P87LPC778FDH Datasheet(HTML) 24 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL