P87LPC778FDH datasheet(25/79 Pages) PHILIPS

25 / 79 page

Philips Semiconductors

P87LPC778

CMOS single-chip 8-bit microcontroller

Product data

Rev. 01 — 31 March 2004

25 of 79

9397 750 12378

8.6.1

PWM brake function

In general when Brake is asserted the four PWM outputs are forced to a user

selected state, namely the state selected by the brakestate in PWMCON1 bits 0 to 3.

As shown in the description of the operation of the PWMCON1 register if

PWMCON1.4 is a ‘1’ brake is asserted under the control PWMCON1.7, BKCH, and

PWMCON1.5, BPEN.

As shown if both are a ‘0’ brake is asserted. If PWMCON1.7 is a ‘1’ brake is asserted

when the run bit, PWMCON0.7, is a ‘0’. If PWMCON1.6 is a ‘1’ brake is asserted

when the Brake Pin, P0.2, has the same polarity as PWMCON1.6. When brake is

asserted in response to this pin the RUN bit, PWMCON0.7, is automatically cleared.

The combination of both PWMCON1.7 and PWMCON1.5 being a ‘1’ is not allowed.

Since the Brake Pin being asserted will automatically clear the Run bit,

PWMCON0.7, the user program can poll this bit to determine when the Brake Pin

causes a brake to occur.

When the brake signal is released, the PWM pins hold their brake state assigned by

PWMCON1[3:0]. Since the RUN bit is cleared, the PWM pins will stay in the brake

state till the PWM is restarted.

The details for PWMCON1 are shown in Tables 20, 21 and 22.

PWM1I

PWM1 output is non-inverted. Output is a ‘1’ from the start

of the cycle until compare; ‘0’ thereafter.

PWM1 output is inverted. Output is ‘0’ from the start of the

cycle until compare; ‘1’ thereafter.

PWM0I

PWM0 output is non-inverted. Output is a ‘1’ from the start

of the cycle until compare; ‘0’ thereafter.

PWM0 output is inverted. Output is ‘0’ from the start of the

cycle until compare; ‘1’ thereafter.

Table 19:

PWMCON0 - PWM control register 0 (address 0DAH) bit description

Bit

Symbol

Value

Description

Table 20:

PWMCON1 - PWM control register 1 (address C8H) bit allocation

Reset value: 00H

Bit

Symbol

BKCH

BKPS

BPEN

BKEN

PWM3B

PWM2B

PWM1B

PWM0B

Table 21:

PWMCON1 - PWM control register 1 (address C8H) bit description

Bit

Symbol

Value

Description

BKCH

See Table 22 below.

BKPS

‘Brake’ is asserted if P0.2 (Brake Pin) is LOW.

‘Brake’ is asserted if P0.2 (Brake Pin) is HIGH.

BPEN

See Table 22 below.

BKEN

‘Brake’ is never asserted.

‘Brake’ is enabled (see Table 22 below).

PWM3B

PWM3 is LOW, when Brake is asserted.

PWM3 is HIGH, when Brake is asserted.

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