PCK9446 datasheet(4/17 Pages) PHILIPS

4 / 17 page

PCK9446_1

Product data sheet

Rev. 01 — 10 April 2006

4 of 17

Philips Semiconductors

PCK9446

2.5 V and 3.3 V LVCMOS clock fan-out buffer

Functional description

Refer to Figure 1 “Logic diagram of PCK9446”.

6.1 Function table

6.2 Supply conﬁgurations

[1]

VCC is the positive power supply of the device core and input circuitry. VCC voltage deﬁnes the input

threshold and levels.

[2]

VCC(bankA) is the positive power supply of the bank A outputs (VCCA pins). VCC(bankA) voltage deﬁnes

bank A output levels.

[3]

VCC(bankB) is the positive power supply of the bank B outputs (VCCB pins). VCC(bankB) voltage deﬁnes

bank B output levels. VCCB is internally connected to VCC.

[4]

VCC(bankC) is the positive power supply of the bank C outputs (VCCC pins). VCC(bankC) voltage deﬁnes

bank C output levels.

Table 3.

Function table (controls)

Control

Default

Value

CLK_SEL

CLK0

CLK1

FSELA

frequency on bank A outputs = fref frequency on bank A outputs = fref ÷ 2

FSELB

frequency on bank B outputs = fref frequency on bank B outputs = fref ÷ 2

FSELC

frequency on bank C outputs = fref frequency on bank C outputs = fref ÷ 2

MR/OE

outputs enabled

internal reset outputs disabled (3-state)

Table 4.

Supported single and dual supply conﬁgurations

Supply voltage

conﬁguration

VCC[1]

VCC(bankA)[2]

VCC(bankB)[3]

VCC(bankC)[4]

GND

3.3 V

0 V

mixed voltage supply

3.3 V

3.3 V or 2.5 V

3.3 V

3.3 V or 2.5 V

0 V

2.5 V

0 V

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