PCK9446_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 10 April 2006

8 of 17

Philips Semiconductors

PCK9446

2.5 V and 3.3 V LVCMOS clock fan-out buffer

[1]

Dynamic (AC) characteristics apply for parallel output termination of 50

Ω to V

[1]

Dynamic (AC) characteristics apply for parallel output termination of 50

[2]

For all other dynamic (AC) specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank.

Table 10.

Dynamic characteristics (2.5 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

reference frequency

input

0

250

-

MHz

maximum output frequency

÷ 1 output; FSELx = 0

0

250

-

MHz

÷ 2 output; FSELx = 1

0

125

-

MHz

reference duty cycle

input

25

-

75

%

LOW-to-HIGH propagation delay

CLKn to any Q

2.2

-

5.0

ns

HIGH-to-LOW propagation delay

CLKn to any Q

2.2

-

5.0

ns

LOW to OFF-state propagation delay

10

ns

HIGH to OFF-state propagation delay

10

ns

OFF-state to LOW propagation delay

10

ns

OFF-state to HIGH propagation delay

10

ns

output skew time

output-to-output

within one bank

-

-

150

ps

any output bank,

same output divider

-

-

200

ps

any output,

any output divider

-

-

1.2

ns

process skew time

part-to-part

-

-

3.0

ns

pulse skew time

output

-

-

500

ps

output duty cycle

45

50

55

%

rise time

input; CLK0, CLK1;

0.7 V to 1.7 V

-

-

3.0

ns

output; 0.6 V to 1.8 V

0.1

-

1.0

ns

fall time

input; CLK0, CLK1;

1.7 V to 0.7 V

-

-

3.0

ns

output; 1.8 V to 0.6 V

0.1

-

1.0

ns

Table 11.

Dynamic characteristics (mixed supply voltages)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

output skew time

output-to-output

within one bank

-

-

150

ps

any output bank; same output divider

-

-

200

ps

any output; any output divider

-

-

1.2

ns

process skew time

part-to-part

-

-

3.0

ns

pulse skew time

output

-

-

500

ps

output duty cycle

÷ 1 or ÷ 2 output; δ

45

50

55

%