PCK9446_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 10 April 2006

6 of 17

Philips Semiconductors

PCK9446

2.5 V and 3.3 V LVCMOS clock fan-out buffer

9.

Static characteristics

[1]

The PCK9446 is capable of driving 50

Ω transmission lines on the incident edge. Each output can drive one 50 Ω parallel terminated

[2]

Input pull-up/pull-down resistors influence input current.

[1]

The PCK9446 is capable of driving 50

Ω transmission lines on the incident edge. Each output can drive one 50 Ω parallel terminated

Table 7.

Static characteristics (3.3 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

CLK0, CLK1; LVCMOS

2.0

-

V

LOW-level input voltage

CLK0, CLK1; LVCMOS

−0.3

-

+0.8

V

HIGH-level output voltage

[1] 2.4

-

-

V

LOW-level output voltage

[1] -

-

0.55

V

-

-

0.30

input current

[2] --

±200

µA

input capacitance

-

4.0

-

pF

power dissipation capacitance

per output

-

10

-

pF

maximum quiescent current

all VCCx pins

-

-

0.5

mA

output impedance

-

(14 to 17)

-

W

termination voltage

output

-

-V

Table 8.

Static characteristics (2.5 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

LVCMOS

1.7

-

V

LOW-level input voltage

LVCMOS

−0.3

-

+0.7

V

HIGH-level output voltage

[1] 1.8

-

-

V

LOW-level output voltage

-

-

0.6

V

input current

-

-

±200

µA

input capacitance

-

4.0

-

pF

power dissipation capacitance

per output

-

10

-

pF

maximum quiescent current

all VCCx pins

-

-

0.5

mA

output impedance

-

(17 to 20)

-

W

termination voltage

output

-

-V