PCK9446_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 10 April 2006

10 of 17

Philips Semiconductors

PCK9446

2.5 V and 3.3 V LVCMOS clock fan-out buffer

The waveform plots of Figure 4 show simulation results of an output driving a single line

versus two lines. In both cases the drive capability of the PCK9446 output buffer is more

than sufficient to drive 50

Ω transmission lines on the incident edge. Note from the delay

measurements in the simulations a delta of only 43 ps exists between the two differently

loaded outputs. This suggests that the dual line driving need not be used exclusively to

maintain the tight output-to-output skew of the PCK9446. The output waveform in Figure 4

shows a step in the waveform; this step is caused by the impedance mismatch seen

looking into the driver. The parallel combination of the 36

Ω series resistor plus the output

impedance does not match the parallel combination of the line impedances. The voltage

wave launched down the two lines will equal:

At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V.

It will then increment towards the quiescent 3.0 V in steps separated by one round trip

delay (in this case 4.0 ns).

Since this step is well above the threshold region it will not cause any false clock

triggering, however designers may be uncomfortable with unwanted reflections on the

line. To better match the impedances when driving multiple lines, the situation in Figure 5

should be used. In this case the series terminating resistors are reduced such that when

the parallel combination is added to the output buffer impedance the line impedance is

perfectly matched.

Fig 4.

Single versus dual waveforms.

V

L

V

S

Z

o

R

s

R

o

Z

o

++

------------------------------





3.0

25

18

17

25

++

------------------------------





1.25 V

==

=

Z

o

50

Ω 50 Ω

R

s

36

Ω 36 Ω

R

o

17

Ω

=

||

=

||

=

time (ns)

016

12

48

002aaa679

3.0

voltage

(V)

−0.5

0

1.0

2.0

IN

OutA

OutB