PCK9446_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 10 April 2006

11 of 17

Philips Semiconductors

PCK9446

2.5 V and 3.3 V LVCMOS clock fan-out buffer

12. Test information

14

Ω +22 Ω|| 22 Ω =50 Ω|| 50 Ω

25

Ω =25 Ω

Fig 5.

Optimized dual line termination

Zo = 50 Ω

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Rs = 22 Ω

Zo = 50 Ω

Rs = 22 Ω

PCK9446

OUTPUT

BUFFER

14

Ω

IN

Zo = 50 Ω

Ro

Fig 6.

Zo = 50 Ω

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RT = 50 Ω

Zo = 50 Ω

RT = 50 Ω

PULSE

GENERATOR

Z = 50

Ω

PCK9446

D.U.T.

The time from the PLL controlled edge to the

non-controlled edge, divided by the time between

PLL controlled edges, expressed as a percentage.

Fig 7.

Output transition time test reference

Fig 8.

Output duty cycle (

The pin-to-pin skew is defined as the worst case

difference in a propagation delay between any

similar delay path within a single device.

Fig 9.

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(1)

(2)

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GND

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Qn

GND

CLK0, CLK1

GND

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GND

GND