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PCK9448 Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCK9448 Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 20 page ![]() 9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 5 of 20 Philips Semiconductors PCK9448 3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer 8.2 Static characteristics [1] VICR (DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the VICR range and the input swing lies within the Vi(p-p) (DC) specification. [2] The PCK9448 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines (VCC = 3.3 V) or one 50 Ω series terminated transmission line (for VCC = 2.5 V). [3] Inputs have pull-down or pull-up resistors affecting the input current. [4] Iq(max) is the DC current consumption of the device with all outputs open and the input in its default state or open. [1] VICR (DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the VICR range and the input swing lies within the Vi(p-p) (DC) specification. [2] The PCK9448 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VT. Alternatively, the device drives one 50 Ω series terminated transmission line per output at VCC = 2.5 V. [3] Inputs have pull-down or pull-up resistors affecting the input current. [4] Iq(max) is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 6: Static characteristics (3.3 V) Tamb = −40 °C to +85 °C; VCC = 3.3 V ± 5 %; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-state input voltage LVCMOS 2.0 - VCC + 0.3 V VIL LOW-state input voltage LVCMOS −0.3 - +0.8 V VOH HIGH-state output voltage IOH = −24 mA [2] 2.4 - - V VOL LOW-state output voltage IOL =24mA [2] - - 0.55 V IOL = 12 mA - - 0.30 V Vi(p-p) peak-to-peak input voltage (PCLK) LVPECL 250 - - mV VICR [1] common-mode input voltage range (PCLK) LVPECL 1.1 - VCC − 0.6 V Zo output impedance - 17 - Ω II input current VI =VCC or GND [3] - - 300 µA Iq(max) maximum quiescent current all VCC pins [4] - - 2.0 mA Table 7: Static characteristics (2.5 V) Tamb = −40 °C to +85 °C; VCC = 2.5 V ± 5 %; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-state input voltage LVCMOS 1.7 - VCC + 0.3 V VIL LOW-state input voltage LVCMOS −0.3 - +0.7 V VOH HIGH-state output voltage IOH = −15 mA [2] 1.8 - - V VOL LOW-state output voltage IOL = 15 mA - - 0.6 V Vi(p-p) peak-to-peak input voltage (PCLK) LVPECL 250 - - mV VICR [1] common-mode input voltage range (PCLK) LVPECL 1.0 - VCC − 0.7 V Zo output impedance - 19 - Ω II input current VI =VCC or GND [3] - - 300 µA Iq(max) maximum quiescent current all VCC pins [4] - - 2.0 mA |
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