PCK9448 datasheet(6/20 Pages) PHILIPS

6 / 20 page

9397 750 12534

Product data sheet

Rev. 01 — 29 November 2005

6 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

8.3 Dynamic characteristics

[1]

Dynamic characteristics apply for parallel output termination of 50

Ω to V

[2]

VICR (AC) is the cross-point of the differential input signal. Normal AC operation is obtained when the cross-point is within the VICR range

and the input swing lies within the Vi(p-p) (AC) speciﬁcation. Violation of VICR or Vi(p-p) impacts static phase offset.

[3]

Setup and hold times are referenced to the falling edge of the selected clock signal input.

[4]

Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference

input pulse width, output duty cycle, and maximum frequency speciﬁcations.

Table 8:

Dynamic characteristics (3.3 V)

Tamb = −40 °C to +85 °C; VCC = 3.3 V ± 5 %; unless otherwise speciﬁed. [1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Vi(p-p)

input voltage (peak-to-peak value)

(PCLK, PCLK)

LVPECL

400

1000

VICR [2]

common-mode input voltage range

(PCLK, PCLK)

LVPECL

1.3

VCC − 0.8 V

output frequency

350

MHz

input frequency

350

MHz

tsk(o)

output skew time

150

tsk(pr)

process skew time

part-to-part

2.0

δo

output duty cycle

fo < 170 MHz; δref = 50 %

tPLH

LOW-to-HIGH propagation delay

PCLK to any Q

1.6

3.6

CCLK to any Q

1.3

3.3

tPHL

HIGH-to-LOW propagation delay

PCLK to any Q

1.6

3.6

CCLK to any Q

1.3

3.3

tPLZ

LOW to OFF-state propagation delay

OE to any Q

tPHZ

HIGH to OFF-state propagation delay

OE to any Q

tPZL

OFF-state to LOW propagation delay

OE to any Q

tPZH

OFF-state to HIGH propagation delay

OE to any Q

tsu

setup time

CCLK to CLK_STOP

[3] 0.0

PCLK to CLK_STOP

[3] 0.0

hold time

CCLK to CLK_STOP

[3] 1.0

PCLK to CLK_STOP

[3] 1.5

rise time

output; 0.55 V to 2.4 V

0.1

1.0

CCLK input; 0.8 V to 2.0 V

1.0 [4]

fall time

output; 2.4 V to 0.55 V

0.1

1.0

CCLK input; 2.0 V to 0.8 V

1.0 [4]

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