1.

General description

The PCK9448 is a 3.3 V or 2.5 V compatible, 1 : 12 clock fan-out buffer targeted for high

performance clock tree applications. With output frequencies up to 350 MHz and output

skews less than 150 ps, the device meets the needs of most demanding clock

applications.

The PCK9448 is specifically designed to distribute LVCMOS compatible clock signals up

to a frequency of 350 MHz. Each output provides a precise copy of the input signal with

near zero skew. The output buffers support driving of 50

Ω terminated transmission lines

on the incident edge: each is capable of driving either one parallel terminated or two

series terminated transmission lines.

Two selectable independent clock inputs are available, providing support of LVCMOS and

differential LVPECL clock distribution systems. The PCK9448 CLK_STOP control is

synchronous to the falling edge of the input clock. It allows the start and stop of the output

clock signal only in a logic LOW state, thus eliminating potential output runt pulses.

Applying the OE control will force the outputs into high-impedance mode.

All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs

from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient

temperature range of

−40 °Cto+85 °C.

2.

Features

applications

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

Rev. 01 — 29 November 2005

Product data sheet