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Product data sheet

Rev. 01 — 29 November 2005

10 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

9.

Application information

9.1 Driving transmission lines

The PCK9448 clock driver was designed to drive high speed signals in a terminated

transmission line environment. To provide the optimum flexibility to the user, the output

drivers were designed to exhibit the lowest impedance possible. With an output

impedance of 17

Ω (V

terminated transmission lines.

In most high performance clock networks, point-to-point distribution of signals is the

method of choice. In a point-to-point scheme, either series terminated or parallel

terminated transmission lines can be used. The parallel technique terminates the signal at

the end of the line with a 50

Ω resistance to 0.5V

level of DC current, and thus only a single terminated line can be driven by each output of

the PCK9448 clock driver. For the series terminated case, however, there is no DC current

draw, thus the outputs can drive multiple series terminated lines. Figure 12, illustrates an

output driving a single series terminated line versus two series terminated lines in parallel.

When taken to its extreme, the fan-out of the PCK9448 clock driver is effectively doubled

due to its capability to drive multiple lines.

Fig 12. Single versus dual transmission lines

Zo = 50 Ω

002aaa722

Rs = 33 Ω

Zo = 50 Ω

Rs = 33 Ω

PCK9448

OUTPUT

BUFFER

OutB1

OutB0

17

Ω

Zo = 50 Ω

Rs = 33 Ω

PCK9448

OUTPUT

BUFFER

OutA

17

Ω

IN

IN

Ro

Ro