Preliminary Technical Data

AD7991/AD7995/AD7999

Rev. PrB | Page 19 of 25

is excessive activity on the interface lines, this may have the effect of increasing the overall conversion time. However, if bit trial delays

extend longer than 1 µs, the conversion terminates.

When Bits D0 and D1 are both 0, the bit trial and sample interval delaying mechanism is implemented. The default setting of D0 and D1

is 0. To turn off both delay mechanisms, set D0 and D1 to 1.

CONVERSION RESULT REGISTER

The conversion result register is a 16-bit read-only register that stores the conversion result from the ADC in straight binary format. A 2-

byte read is necessary to read data from this register. Table 12 shows the contents of the first byte to be read, from

AD7991/AD7995/AD7999 and Table 13 shows the contents of the second byte to be read.

Table 12. Conversion Value Register (First Read)

D15

D14

D13

D12

D11

D10

D9

D8

Leading Zero

Leading Zero

MSB

B10

B9

B8

Table 13. Conversion Value Register (Second Read)

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3 /0

B2 /0

B1/0

B0/0

The AD7991/AD7995/AD7999 conversion result consists of 2 leading zeros, two channel identifier bits, and the 12-/10-/8- bit data result.

For the AD7995, the 2 LSB (D1 and D0) of the second read contain two trailing 0s. For the AD7999, the 4 LSB (D3, D2, D1 and D0) of

the second read contain 4 trailing zeros