AD8382 datasheet(13/24 Pages) AD

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AD8382

Rev. 0 | Page 13 of 24

FUNCTIONAL DESCRIPTION

The AD8382 is a system building block designed to directly

drive the columns of LCD microdisplays of the type

popularized for use in projection systems. It comprises six

channels of precision, 12-bit digital-to-analog converters loaded

from a single, high speed, 12-bit wide input. Precision current

feedback amplifiers, providing well-damped pulse response and

fast voltage settling into large capacitive loads, buffer the six

outputs. Laser trimming at the wafer level ensures low absolute

output errors and tight channel-to-channel matching. Tight

part-to-part matching in high resolution systems is guaranteed

by the use of external voltage references.

V1, V2 INPUTS—VOLTAGE REFERENCE INPUTS

Two external analog voltage references set the levels of the

outputs. V1 sets the output voltage at Code 4095 while the INV

input is LOW, and V2 sets the output voltage at Code 4095 while

the INV input is held HIGH.

VREFHI, VREFLO INPUTS—FULL-SCALE

REFERENCE INPUTS

Twice the difference between these analog input voltages sets

the full-scale output voltage VFS.

START SEQUENCE CONTROL—INPUT DATA

VFS

= 2 × (VREFHI – VREFLO)

INV CONTROL—ANALOG OUTPUT INVERSION

A valid STSQ control input initiates a new 6-clock loading

cycle, during which six input data-words are loaded sequentially

into six internal channels. A new loading sequence begins on

the current active CLK edge only when STSQ was held HIGH at

the preceding active CLK edge. Active CLK edge is defined by

the E/O Control.

The analog voltage equivalent of the input code is subtracted

from (V2 + VFS) while INV is held HIGH and added to (V1 –

VFS) while INV is held LOW.

Transfer Function

The AD8382 has two regions of operation, where the video

output voltages are either above reference voltage V2 or below

reference voltage V1. The transfer function defines the video

output voltage as the function of the digital input code as

follows:

EVEN/ODD CONTROL—INPUT DATA LOADING

To facilitate 12-channel, single data bus systems, the active CLK

edge, at which input data is loaded, is selected with the E/O

control input. Input data is loaded on the rising CLK edges

while the E/O input is held HIGH; input data is loaded on the

falling CLK edges while the E/O input is held LOW.

VIDx

(n) = V2 + VFS × (1 – n/4095), for INV = HIGH

VIDx

(n) = V1 – VFS × (1 – n/4095), for INV = LOW

RIGHT/LEFT CONTROL—INPUT DATA LOADING

where n = input code

To facilitate image mirroring, the direction of the loading

sequence is set by the R/L control. A new loading sequence

begins at channel 0 and proceeds to Channel 5 when the R/L

control is held LOW. It begins at Channel 5 and proceeds to

channel 0 when the R/L control is held HIGH.

VFS

= 2 × (VREFHI – VREFLO)

A number of internal limits define the usable range of the video

output voltages, VIDx, as shown in Figure 36

INPUT CODE

AGND

V1–VFS

V2+ VFS

AVCC

4095

≤ VFS ≤ 5.5V

≤ V2 ≤ (AVCC – 4)

≤ V1 ≤ (AVCC – 4)

≤ AVCC ≤ 18V

≥ 1.3V

INV = HIGH

INV = LOW

INTERNAL LIMITS AND

USABLE VOLTAGE RANGES

XFR CONTROL—DATA TRANSFER TO OUTPUTS

Data transfer to the outputs is initiated by the XFR control.

While XFR is held HIGH during a rising CLK edge, data is

simultaneously transferred to all outputs on the immediately

following falling CLK edge.

STBY CONTROL—STANDBY MODE

A HIGH applied to the STBY input debiases the internal

circuitry, dropping the quiescent power dissipation to a few

milliwatts. Upon returning STBY to LOW, normal operation is

restored. Since both analog and digital circuitry is debiased, all

stored data will be lost in standby mode.

Figure 36. Transfer Function and Usable Voltage Ranges

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