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MAX5322 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX5322 Datasheet(HTML) 6 Page - Maxim Integrated Products |
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6 / 18 page  ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC 6 _______________________________________________________________________________________ TIMING CHARACTERISTICS (VDD = +15V, VSS = -15V or 0V, VCC = +2.7V to +5.5V, AGND = DGND = SGND_ = 0, VREF_ = 5V, RLOAD = 2k Ω, ,CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 °C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Frequency 10 MHz SCLK Clock Period tCP 100 ns SCLK Pulse-Width High tCH For nondaisy-chain use 45 ns For nondaisy-chain use 45 SCLK Pulse-Width Low tCL For daisy-chain use 98 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns +2.7V ≤ VCC ≤ +3.6V 15 SCLK Rise to CS Rise Hold Time tCSH +4.5V ≤ VCC ≤ +5.5V 10 ns DIN Setup Time tDS 20 ns DIN Hold Time tDH 10 ns LDAC Pulse Width tLD 50 ns +2.7V ≤ VCC ≤ +3.6V 100 CS Rise to LDAC Low Setup Time tLDS +4.5V ≤ VCC ≤ +5.5V 50 ns CLOAD = 20pF, +2.7V ≤ VCC ≤ +3.6V 100 SCLK Fall to DOUT Valid Propagation Delay tDO1 CLOAD = 20pF, +4.5V ≤ VCC ≤ +5.5V 80 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Low to DOUT Valid Time tCSE CLOAD = 20pF 120 ns CS High to DOUT Disabled Time tCSD 120 ns CS Rise to SCLK Rise Hold Time tCS1 50 ns +2.7V ≤ VCC ≤ +3.6V 200 CS Pulse-Width High tCSW +4.5V ≤ VCC ≤ +5.5V 100 ns CLR Pulse-Width Low tCLR 50 ns Note 1: Output unloaded, digital inputs = VCC or DGND. Note 2: ∆VDD = 15.5V to 14.5V, ∆VSS = -15.5V to -14.5V, input code = 14hex to FFFhex Note 3: Accuracy is guaranteed from code 14hex to FFFhex |
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