CDB42406 datasheet(6/32 Pages) CIRRUS

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CDB42406

1.7.1

S/PDIF IN & S/PDIF OUT (Setup 0 - Setup 2)

There are 3 different setup options for routing MCLK, LRCK and SCLK for S/PDIF input

and output conversion. These options allow the user to choose between 3 different mas-

ters for the ADC subclocks. Should the CS8416 lose lock to the S/PDIF input, the RMCK

will automatically switch from the PLL to the OMCK input (see the CS8416 datasheet for

details). The CS8406 is always clocked from the same source as the ADC.

1.7.1a

Setup 0

Using the recovered clock from the S/PDIF input data stream, the CS8416 masters all

clocks for the ADC and all clocks and data for the DAC. For implementation of this setup

option, set DIP switch S4 (SW[3:0]) to ‘0000’b.

AU DIO

MCLK

MC LK

DAC_L RCK/

DAC_SC LK

AD C_ LR CK/

AD C_ SC LK

DAC_SD IN x

ADC _SD OU T

C S42406

DSP I/O

HDR

D SP_MC LK

D SP_AD C_ LRC K/

D SP_AD C_ SC LK

DSP_SD OU T

DSP_DAC_ LRCK/

D SP_D AC_ SC LK

DSP_SD IN x

CS8406

CS8416

RM CK

OM CK

OLR CK/

OSC LK

SD OU T

OM CK

IL RC K/

ISC LK

SDIN

Figure 1. S/PDIF IN/OUT - Setup 0

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