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CDB42406 Datasheet(PDF) 8 Page - Cirrus Logic |
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CDB42406 Datasheet(HTML) 8 Page - Cirrus Logic |
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8 / 32 page ![]() CDB42406 8 1.7.2 Digital Loopback (Setup 3 - Setup 6) There are 4 different setup options for routing MCLK, LRCK and SCLK for digital loop- back. These setup configurations allow analog input/output analysis without the need for a digital signal analyzer/source. These options also allow the user to choose between 2 different MCLK and 2 different subclock sources for the ADC/DAC. 1.7.2a Setup 3 Using the on-board crystal oscillator, AUDIO MCLK, the CS42406 ADC masters the sub- clocks and data for the DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0011’b. AU DIO MCLK MCLK D AC_LRCK/ DAC_SCLK ADC _LRC K/ ADC _S CLK DAC_SDINx ADC_SD O UT CS42406 D SP I/O HDR DSP _MC LK DS P_ADC_LRCK / DS P_ADC_SC LK DSP _SDO UT DS P_DAC_LRCK / DS P_DAC_SC LK DSP_SD INx C S8406 CS8416 RM CK OM CK OLR CK/ OS CLK SDO UT OMC K ILRC K/ ISC LK SDIN Figure 4. Digital Loopback - Setup 3 |
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