TJ = TB + ψJB × PD

(10)

where:

• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application note.

8.3 Best Design Practices

Place at least one 0.47-µF capacitor as close as possible to the OUT and GND pins of the regulator.

Do not connect the output capacitor to the regulator using a long, thin trace.

Connect an input capacitor as close as possible to the IN and GND pins of the regulator for best performance.

Do not exceed the absolute maximum ratings.

8.4 Power Supply Recommendations

The TLV709 is designed to operate from an input voltage supply range between 2.5 V and 30 V. The input

voltage range provides adequate headroom in order for the device to have a regulated output. If the input supply

is noisy, additional input capacitors with low ESR can help improve the output noise performance.

8.5 Layout

8.5.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the printed circuit board (PCB)

and as near as practical to the respective LDO pin connections. Place ground return connections for the input

and output capacitors as close to the GND pin as possible, using wide, component-side, copper planes. Do

not use vias and long traces to create LDO circuit connections to the input capacitor, output capacitor, or the

resistor divider because this practice negatively affects system performance. This grounding and layout scheme

minimizes inductive parasitics, and thereby reduces load current transients, minimizes noise, and increases

circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located

on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the

output voltage and shield the LDO from noise.

8.5.1.1 Power Dissipation

To ensure reliable operation, worst-case junction temperature must not exceed 125°C. This restriction limits the

power dissipation the regulator can handle in any given application. To ensure the junction temperature is within

acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which

must be less than or equal to PD(max).

Equation 11 determines the maximum-power-dissipation limit:

J

A

D(max)

JA

T max T

P

R

q

-

=

(11)

where:

• TJmax is the maximum allowable junction temperature

• RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Informationtable)

• TA is the ambient temperature

Equation 12 calculates the regulator dissipation:

D

IN

OUT

OUT

P

(V

V

) I

=

-

´

(12)

www.ti.com

TLV709

SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023

Copyright © 2023 Texas Instruments Incorporated

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Product Folder Links: TLV709