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TLV709 Datasheet(PDF) 5 Page - Texas Instruments |
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TLV709 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 31 page ![]() 6.4 Thermal Information THERMAL METRIC(1) TLV709 (2) UNIT DBV [SOT-23] PK [SOT-89] 5 PINS 4 PINS RθJA Junction-to-ambient thermal resistance 195.7 131.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 88.2 65.8 °C/W RθJB Junction-to-board thermal resistance 40.7 32.4 °C/W ψJT Junction-to-top characterization parameter 11.2 69.8 °C/W ψJB Junction-to-board characterization parameter 40.5 96.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. (2) Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. www.ti.com TLV709 SLVSGU2B – FEBRUARY 2023 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV709 |
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