LPC804_V02 datasheet(24/89 Pages) NXP

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LPC804

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Product data sheet

Rev. 2.1 — 25 July 2023

24 of 87

NXP Semiconductors

LPC804

32-bit Arm Cortex-M0+ microcontroller

9.18 Windowed WatchDog Timer (WWDT)

The watchdog timer resets the controller if software fails to service the watchdog timer

periodically within a programmable time window.

9.18.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in

multiples of Tcy(WDCLK)  4.

• The WatchDog Clock (WDCLK) is generated by the dedicated watchdog oscillator

(WDOSC).

9.19 Self-Wake-up Timer (WKT)

The self-wake-up timer is a 32-bit, loadable down counter. Writing any non-zero value to

this timer automatically enables the counter and launches a count-down sequence. When

the counter is used as a wake-up timer, this write can occur prior to entering a reduced

power mode.

9.19.1 Features

• 32-bit loadable down counter. Counter starts automatically when a count value is

loaded. Time-out generates an interrupt/wake up request.

• The WKT supports three clock sources: an external clock on the WKTCLKIN pin, the

low-power oscillator, and the FRO. The low-power oscillator can be used as the clock

source in sleep, deep-sleep, and power-down modes.

• The WKT can be used for waking up the part from any reduced power mode or for

general-purpose timing.

9.20 Programmable Logic Unit (PLU)

The PLU is comprised of 26 5-input LUT elements. Each LUT element contains a 32-bit

truth table (look-up table) register and a 32:1 multiplexer. During operation, the five LUT

inputs control the select lines of the multiplexer. This structure allows any desired logical

combination of the five LUT inputs.

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