| Electronic Components Datasheet Search |
|
CS5535 Datasheet(PDF) 494 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
CS5535 Datasheet(HTML) 494 Page - National Semiconductor (TI) |
|
494 / 555 page ![]() www.national.com 494 Revision 0.8 PMC Register Descriptions (Continued) 5.18.3.12 PM De-assert Reset Delay from Standby (PM_RD) Reads always return the value written, except for RSVD bits [29:20]. 30 WORK_AUX_ DEASSERT_EN Working Auxiliary De-assert and Delay Enable. Must be high to de-assert the WORK_AUX output and enable its delay specified in bits [19:0] (WORK_AUX_DEASSERT_DELAY). Use of this control implies a system sequence into the Standby State. The PMC dis- ables its interfaces to non-Standby portions of the component and only considers wakeup events from Standby circuits. The PMC also immediately asserts system reset when SLP_CLK_EN# is asserted regardless of the value of WORK_AUX_DEASSERT_DELAY (bits [19:0]). Reset remains asserted throughout the Standby state. There is NOT an assert delay. The wakeup event causes the WORK_AUX output to assert. This event is called Standby wakeup. On wakeup, Reset continues to be applied to all non-Standby circuits for the length of time specified in RESET_DELAY (PMS I/O Offset 38h[19:0]). Enabling this function and/or the function in PM_WKD (PMS I/O Offset 30h[30] = 1) causes the same Standby state events. Standby state is not entered unless SLP_CLK_EN# is asserted. 29:20 RSVD Reserved. By convention write 0, but may write anything. Reads return 0. 19:0 WORK_AUX_ DEASSERT_ DELAY WORK_AUX De-assert Delay. Indicates the number of 32 kHz clock edges to wait from the assertion of SLP_CLK_EN# before de-asserting the WORK_AUX output. Bit 30 (WORK_AUX_DEASSERT_EN) must be high to enable this delay. PMS I/O Offset 38h Type R/W Reset Value 40000100h PM_RD Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 RSVD RESET_DELAY PM_RD Bit Descriptions Bit Name Description 31 RESET_LOCK Reset Lock. After this bit is set, the value in this register can not be changed until RESET_STAND# is applied. 30 RESET_EN Reset Delay Enable. Must be high for the RESET_OUT# output de-assert delay spec- ified in bits [19:0] (RESET_DELAY) to be applied. (Default = 1.) 29:20 RSVD Reserved. By convention write 0, but may write anything. Reads return 0. PM_WKXD Bit Descriptions Bit Name Description |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |