CS5535 datasheet(490/555 Pages) NSC

490 / 555 page

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490

Revision 0.8

PMC Register Descriptions (Continued)

5.18.3.6

PM Sleep End Delay (PM_SED)

Reads always return the value written.

5.18.3.7

PM Sleep Control X De-assert Delay (PM_SCXD)

Reads always return the value written.

PMS I/O Offset

14h

Type

R/W

Reset Value

00000000h

PM_SED Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

SLPEND_DELAY

PM_SED Bit Descriptions

Bit

Name

Description

RSVD

Reserved. By convention write 0, but may write anything.

SLPEND_EN

Sleep End Delay Enable. Must be high to enable the delay specified in bits [29:0]

(SLPEND_DELAY).

29:0

SLPEND_DELAY

Sleep End Delay. Indicates the number of 3.57954 MHz clock edges to wait from

Sleep wakeup before de-asserting SUSP#. Bit 30 (SLPEND_EN) must be high to

enable this delay.

If PCI_IDE_IN_SLP is not enabled (PMS I/O Offset 20h[30] = 0) or the delay is less

than SLPEND_DELAY, SUSP# de-asserts at the same time the PCI/IDE inputs are re-

enabled.

PMS I/O Offset

18h

Type

R/W

Reset Value

00000000h

PM_SCXD Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

SLPX_END_DELAY

PM_SCXD Bit Descriptions

Bit

Name

Description

RSVD

Reserved. By convention write 0, but may write anything.

SLPX_END_EN

Sleep X De-assert and Delay Enable. Must be high to de-assert SLEEP_X and

enable the delay specified in bits [29:0] (SLPX_END_DELAY).

CS5535 Datasheet(PDF) 490 Page - National Semiconductor (TI)

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