CS5535 datasheet(488/555 Pages) NSC

488 / 555 page

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488

Revision 0.8

PMC Register Descriptions (Continued)

5.18.3.3

PM Sleep Control Y Assert Delay and Enable (PM_SCYA)

Reads always return the value written.

5.18.3.4

PM Sleep Output Disable Assert Delay and Enable (PM_OUT_SLPCTL)

Reads always return the value written.

29:0

SLPX_DELAY

Sleep X Assert Delay. Indicates the number of 3.57954 MHz clock edges to wait from

the assertion of SUSPA# before asserting the SLEEP_X ball. Bit 30 (SLPX_EN) must

be high to enable this delay.

SLEEP_X is not allowed to assert if this delay is larger than SLPCLK_DELAY (PMS

I/O Offset 10h[29:0]). This is only true if SLPCLK_EN is enabled (PMS I/O Offset

10h[30] = 1).

PMS I/O Offset

08h

Type

R/W

Reset Value

00000000h

PM_SCYA Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

SLPY_DELAY

PM_SCYA Bit Descriptions

Bit

Name

Description

RSVD

Reserved. By convention write 0, but may write anything.

SLPY_EN

Sleep Y Assert and Delay Enable. Must be high to assert SLEEP_Y and enable its

assert delay specified in bits [29:0] (SLPY_DELAY).

29:0

SLPY_DELAY

Sleep Y Assert Delay. Indicates the number of 3.57954 MHz clock edges to wait from

the assertion of SUSPA# before asserting the SLEEP_Y ball. Bit 30 (SLPY_EN) must

be high to enable this delay.

SLEEP_Y is not allowed to assert if this delay is larger than SLPCLK_DELAY (PMS

I/O Offset 10h[29:0]). This is only true if SLPCLK_EN is enabled (PMS I/O Offset

10h[30] = 1).

PMS I/O Offset

0Ch

Type

R/W

Reset Value

00000000h

PM_OUT_SLPCTL Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

PCI_IDE_OUT_SLP_DELAY

PM_SCXA Bit Descriptions (Continued)

Bit

Name

Description

CS5535 Datasheet(PDF) 488 Page - National Semiconductor (TI)

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